Large-scale commodity computing coupled with services purchased over the internet (e.g. Software as a Service, SaaS),
aka the cloud, are shifting the computing paradigm once again. Integrated circuit, package and board design is certainly being
affected by this change and will, to some extent, migrate from workstations and corporate servers to the cloud.
The effect of this change goes beyond the mere convenience of web-hosted design software and is profound.
The main driving forces are cost-effectiveness and the exploitation of massive parallelism: The cloud gives the illusion of unlimited
resources for a given amount of time, providing access to unprecedented capacity and speed on a pay-per-use basis. Over time
a new generation of design technology, written from the ground up with parallelism and the cloud in mind, will emerge.
This paper explores these issues in general, and examines a particularly good match for the cloud, namely electromagnetic field simulation.
Short vita of Raul Camposano:
Raul has over 25 years of experience in electronics and design technology with careers in industry and academia.
He is currently the CEO of Physware, a startup developing design technology for the cloud.
Until 2009 he was President and CEO of Xoomsys. From 1994 to 2007 he was with Synopsys, where he served as Chief Technology Officer,
Senior Vice President, and General Manager for multiple Business Units. Prior to joining Synopsys,
Raul was a Director for the German National Research Center for Computer Science,
Professor of Computer Science at the University of Paderborn, and a Research Staff Member at the IBM T.J. Watson Research Center.
Raul holds a B.S and M.S. in Electrical Engineering from the University of Chile, and a Ph.D. in Computer Science from the University
of Karlsruhe. He has published over 70 technical papers and written and/or edited three books on electronic design automation.
Skilled as a businessperson, a researcher and a teacher, Raul has contributed significantly to building the design community as a whole.
He serves on numerous editorial, advisory and company boards. Raul was also an Advisory Professor at Fudan University and the
Chinese Academy of Sciences. He was elected a Fellow of the IEEE in 1999.
Cost Effective Scaling to 22nm and Below Technology Nodes|
Andrzej J. Strojwas
PDF Solutions, Inc. and Carnegie Mellon University
Pittsburgh, PA15213, USA
>> Conference Program
For decades, Moore’s law transistor cost scaling created a vibrant ecosystem of foundries, fabless design houses, IDMs, and suppliers.
Each of these parties shared in the abundant economic benefits of the transistor cost scaling enabled by Moore’s law. This led to specialization
within each layer and vertical segment of the supply chain wherein rigid technical interfaces allowed uni-dimensional technology trajectories to
thrive. As we approach the challenges of achieving economic scaling at 22nm and beyond, we are confronted with a new set of challenges that will
require tighter integration along historically rigid interfaces. This environment sets the stage for the pendulum to swing toward technologies that
take advantage of tighter coupling between layout architectures and process capabilities, and between process control needs and product sensitivities.
Taking the next step in Moore’s law with the application of smarter and more efficient circuit, layout, and lithography co-design techniques that
can provide high density and increased yields at a sustainable cost. The key enabler of this methodology is the creation of a regular design fabric
onto which one can efficiently map the selected templates using a limited number of printability-friendly layout patterns. The co-optimization of
circuit, layout, and process is achieved by co-developing circuit functions, layout pattern library and lithography solutions. This solution replaces
design rules for logic with a rigorously characterized set of layout Templates. We will demonstrate that this methodology will enable future
technology nodes that utilize current generation lithography while minimizing the cost per good die. In particular, we will: discuss the choice of
regular design fabrics and their implications on design metrics, yields and cost; show that the selection of circuit topologies can be mapped efficiently
to the choice of regular design fabric, and compare lithography solutions such as double patterning (DPT), direct write multi-e-beam (MEBM) and
interference lithography (IL) for the 22nm technology node and beyond.
Short vita of Andrzej J. Strojwas
ANDRZEJ J. STROJWAS is Joseph F. and Nancy Keithley Professor of Electrical and Computer Engineering at Carnegie Mellon University. Since 1997 he
has served as Chief Technologist at PDF Solutions, Inc. He has held positions at Harris Semiconductor Co., AT&T Bell Laboratories, Texas Instruments,
NEC, HITACHI, SEMATECH, KLA-Tencor and PDF Solutions, Inc. He received multiple awards for the best papers published in the IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Semiconductor Manufacturing and IEEE-ACM Design Automation Conference.
He is also a recipient of the SRC Inventor Recognition Award. He was the Editor of the IEEE Transactions on CAD of ICAS from 1987 to 1989.
He served as Technical Program Chairman of the 1988 ICCAD and Conference Chairman of the 1989 ICCAD. In 1990 he was elected IEEE Fellow.
Future of EDA: Usual Suspect or Silent Hero for Successful Semiconductor Business?|
Intel Mobile Communications GmbH, Am Campeon 10-12, 85579 Neubiberg, Germany
>> Conference Program
During history of semiconductor development Computer-Aided Design developed into Electronic Design Automation. Point tools provided by CAD/EDA industry were selected by industrial design flows and integrated to make use of best-in class tools available for product development. This was a useful approach to target the classical focus segments for semiconductor design: area, verification and technology enabling. During the last years additional design parameters like power optimization have been introduced successfully into industrial design flows. There is still a need to improve tools addressing these technical design constraints within the foreseeable future.
Main focus of future design flows have to be on additional business constraints like overall manufacturing cost and Time-to-Volume. The world of semiconductor business has changed significantly during the last years. Product development is globally distributed. Value chain from specification to development to manufacturing is split-up over various countries and continents. Supply chain to customers requires more flexibility. Market window for most of the products is getting smaller and smaller.
Design-for-Test may serve as an example for linking design and manufacturing disciplines within semiconductor development. This discipline covers design teams and test engineering. To control Time-to-Volume and Cost-of-Yield of a product, production engineering teams need effective diagnosis environment linking data bases from design, test engineering and manufacturing sites. This example shows the required borderless approach to be addressed by future EDA tools.
Short vita of Jürgen Alt:
Since February 2011 Jürgen Alt is responsible for Design-for-Test flows and implementation within Intel Mobile Communications. IMC is former Infineon’s wireless communications unit and conducted as stand-alone business within Intel.
Jürgen Alt is working in fields Design & Test, EDA-Software and Reliability since 20 years. He holds a diploma in electrical engineering and graduated as Dr.-Ing. from University of Hannover in 1995. Afterwards he joined Siemens Semiconductors Group (now Infineon Technologies AG). Here he owned various line and project management positions in design flow and product test departments. He is senior member of IEEE and German VDE.